1. Field of the Invention
The present invention is in the field of motor controller and positioning servo loops. The present invention further relates to Hard Disk Drive and optical data storage devices. The present invention further relates to methods and circuits for controlling a voice coil motor for positioning the read/write head of a hard disk drive. The implementation is not limited to a specific technology, and applies to either the invention as an individual component or to inclusion of the present invention within larger systems which may be combined into a larger integrated circuit.
The invention also falls within the field of Digital to Analog Converters and more specifically, the invention falls into the class of converters referred to as oversampling Digital to Analog and Analog to Digital Converters.
2. Brief Description of Related Art
The position of the read/write head of a disk drive is typically controlled by a linear motor, often referred to as the Voice Coil Motor (VCM). The VCM 4, as shown in FIG. 1, is represented as an inductor L1 in series to a resistor R1 to indicate the main electrical parameters of the motor. The VCM is driven in response to a control loop, known as the servo loop, whose main algorithm is implemented typically within a microprocessor 1 or similar digital processor, and is typically driven in at least three different modes.
A “seek” mode causes the read/write head to move from one track on the disk to a potentially unrelated track, which may require a significant motion. In this mode, the control system typically attempts to control the velocity of the mechanism. In a “track follow” mode, the read/write head is relatively stationary, and the control system works to control its precise position to be directly above the appropriate track. In a third mode, the head is driven onto or off of the disk surface to a “park” position, typically using a mechanical ramp to pull the head above the plane of the disk.
As shown in FIG. 1, the servo positioning control loop comprises a microprocessor 1 that contains the main servo algorithm and that drives, with digital signals, a digital to analog converter (DAC) 2. This DAC 2 typically drives a VCM actuator 3 in its various forms and implementations. The VCM actuator 3 commands the current into the VCM 4 which defines its arm's velocity and position on the disk surface. A magneto-resistive head 5, situated on the extremity of the VCM arm, and a pre-amplifier device 6, located next to the head, detect and amplify the electrical pulses associated with the magnetic data written on the disk.
The signal from the pre-amplifier is fed into the read-write channel device 7 that deciphers the pulses and converts them into digital words for the microprocessor 1. These digital words include the data written to and read from the disk and the positioning signal 9. Ono et al. (U.S. Pat. No. 6,216,050) shows an equivalent solution.
In addition to the servo loop there is typically an inner analog current control loop that drives the VCM as shown in more details in FIG. 2. The microprocessor 1 drives a Digital to Analog converter 2 which, in its turn, commands the current through the inner current control loop. In this case the VCM actuator block 3 comprises the inner analog current control loop to regulate the current into the VCM 4.
In order to give optimal control, the overall servo loop commands a particular current to be driven into the VCM, and an inner analog control loop actually regulates the current. Practical circuit implementation considerations require that the VCM be driven with conventional amplifiers which force a voltage across the VCM. The local analog control loop senses the current in the VCM, compares it to the commanded current, and adjusts the drive voltage to maintain the desired current.
The inner analog loop is driven by a DAC 2 creating an analog representation of the digitally commanded current, and a Current Sense Amplifier (CSA) 13 generates a signal representing the value of the VCM current. These two signals are summed out of phase in summer 10, such that its output is the error in the present value of the current.
The summer 10 output feeds an amplifier stage generally referred to as the error amplifier 11. This stage is conventionally an integrator, with arbitrarily high gain at DC but with gain falling with frequency to maintain the stability of the loop at higher frequencies. This stage might also implement additional frequency/phase shaping for stability. The output of error amplifier 11 feeds the VCM power amplifier 12, typically two anti-phase linear amplifiers, connected as a “full bridge” capable of imposing the full supply voltage across the load in either polarity. In series with the VCM 4 there is a small resistor R5 used to sense current. The voltage across this current sense resistor R5 is used as the differential input to the current sense amplifier 13. Schillaci et al. (U.S. Pat. No. 6,417,639) provided an equivalent solution.
Within this loop, the error amplifier is a standard operational amplifier. Small DC errors can be initialized out of the loop with software, and the AC requirements are easily met with conventional design techniques. The VCM power amplifier 12 is similarly very conventional in design, and is not appreciably different from an audio amplifier used to drive a loudspeaker load. Because it is embedded within the high gain inner loop, this stage does not contribute to errors in the servo loop.
The two components of this analog loop that require precision analog design are the current sense amplifier and the DAC. The current sense amplifier's DC error may be calibrated out of the system through parameters in the overall digital control loop. But a large common mode error would be difficult to similarly calibrate out. As the VCM is driven through the extremes of its range, the small signal across the sense resistor also is moved common mode through the entire range. Any failure in the current sense amplifier to reject this common mode signal will result in false detection of VCM current.
The DAC is typically on the order of 12–14 bits, representing a total dynamic range of 70–80 dB. This dynamic range is critical in order to be able to control both very large currents needed to sweep the head across the disk quickly and to control the head position without error over a very small final position (within the disk track). The design of conventional DACs (also known as Nyquist-rate DACs) with this resolution is well known in the art, but the appropriate design techniques take up considerable silicon and nevertheless may have a finite yield loss when tested for accuracy. For high accuracy and speed, standard techniques also consume significant power. The testing of the main parameters of the DACs (like integral and differential non-linearity and monotonicity), also represents a considerable cost in the manufacturing process.
The overall analog control system, including DAC, current sense amplifier, error amplifier and power amps is typically implemented on a single chip, as in Kagami et al. (U.S. Pat. No. 6,678,109), usually along with the control and power for the disk's spindle motor and any other analog/power functions required in the chip. The resultant “combo chip” has a yield which is a product of the yield of all of the subsystems, so any subsystem which carries a risk of yield loss due to performance variation is of great concern in the analysis of system cost.
It is well known in the art that the DAC can be replaced with a pulse-width modulated signal. Such a PWM DAC was common in the past when system requirements were significantly reduced compared to modern systems. In order to pass a particular signal bandwidth, a PWM waveform that switches somewhat faster than twice that rate must be developed. In order to simply generate a PWM waveform from an n-bit binary word, a clock 2^n times the switching frequency is needed. If, for instance, it were desired to use a PWM waveform at 20 kHz (so as to be at frequencies higher than the audible band) and to be 14 bits, the required digital clock would need to be 328 MHz, which is a plausible but not entirely practical. This modulation would create a signal, including the desired base-band component, plus the spectrum of a large signal switching waveform at 20 kHz with many harmonics up to very high frequency.
It is also known, that in signal conversion fields, where high accuracy and signal dynamic are necessary, alternate “oversampling” converters and more specifically “one-bit” converters have significant advantage over simple PWM schemes. One of these schemes is the sigma-delta modulator, also known as a delta-sigma modulator. The sigma-delta modulator is, in its most conventional form, a servo loop that controls an analog bitstream such that its average value (between output low and output high) is forced to be proportional to an analog input value. This generally forms an analog to digital conversion. Traditionally in an analog to digital converter, the single bit high frequency bitstream is then processed through digital filtering to create a multibit low frequency data-stream.
It is also known that this sigma-delta architecture can be used to convert a digital input into the same output bitstream by replacing the servo loop with direct digital implementations of the same loop, giving a conversion from a relative low frequency sequence of multi-bit digital values (analogous to the analog input) to a higher frequency single bit bitstream that has a time average value proportional to the input numerical values.
Unlike the PWM coder which has a dynamic range proportional to the ratio of the high frequency clock to the switching frequency (the over-sampling ratio, OSR), the sigma-delta converter has a dynamic range that increases with the over-sampling ratio raised to the power of 1.5. Higher order loops, which contain cascades of integrator stages, further increase the rate at which dynamic range increases with OSR.
A high frequency bitstream that is 1000 times the highest frequency of interest can have a signal to noise ratio (SNR) of 90 dB with a first order sigma-delta, whereas for the PWM DAC would be only 60 dB. The high frequency out-of-band noise in the PWM signal would be centered at twice the maximum signal frequency, the high frequency noise in the sigma-delta case is effectively random noise that increases with frequency and then is spread evenly across a wide bandwidth, easily filtered from the main signal.
In the Hard Disk Drive (HDD) systems the density of the magnetic data recorded on the disk is increasing very rapidly and that is translated in the number of rotational tracks per inch on the disk surface. The tracks containing the magnetic data are consequently getting narrower and the burden to stay on track with limited Bit Error Rate (BER) during normal operation, is shifted to the ability to control the position of the head on the disk with increasing accuracy.
Accordingly, what is needed is a VCM DAC that is cost-effective, easier to implement and with better performance in terms of dynamic range in order to improve the control of VCM and, consequently, the control of the position of the read/write head on the disk.